Job Title: Verification Engineer

Job Location: Hyderabad

Experience: 5 to 8 years

Education: B.E./B.Tech/M.E./M.Tech in ECE, Electrical, or VLSI Design or equivalent

:

we are seeking a Verification Engineer specializing in Static Timing Analysis (STA) and Standard Cell Characterization for advanced memory product development (HBM, DRAM). The role involves working closely with cross-functional design and verification teams to ensure robust, high-performance memory solutions.

Responsibilities:

- Perform Static Timing Analysis at block, cell, and full-chip levels for DRAM/memory designs.
- Characterize standard cells (up to 40% effort) using PrimeLib, SiliconSmart
- Create and validate .lib files, write ARC for cell characterization, and run QA checks.
- Develop timing constraints, analyze STA reports, and ensure violation closure.




- Collaborate with design teams on parasitic modeling, validation experiments, and tape-out revisions.
- Drive standardization across verification flows and contribute to innovation in next-gen memory products.

Mandatory Skills:

- STA tools (Synopsys PrimeTime / Cadence Tempus)
- Standard Cell Characterization (.lib, ARC, QA)
- Robust circuit understanding (digital/analog mix, block to full-chip)
- Timing constraints and violation debug

Good to Have:

- TSMC process certification
- Low-power timing closure experience
- Scripting (TCL, Python, Perl)
- Parasitic modeling exposure
- Hands-on with reticle experiments or silicon validation

📌 Verification Engineer || VLSI (Hyderabad)
🏢 Acesoft Labs
📍 Hyderabad