Senior Emulation Engineer – Palladium / ZeBu

Location: Bengaluru, Karnataka

Experience: 6+ Years

Notice Period: 0–30 Days preferred

Role Overview

We are looking for an experienced Senior Emulation Engineer with strong hands-on experience in Cadence Palladium and/or Synopsys ZeBu platforms. The role involves pre-silicon SoC verification, hardware emulation, debug, and validation of complex designs.

Responsibilities

- Develop and execute hardware emulation environments for complex SoC/ASIC designs.
- Work hands-on with Cadence Palladium and/or Synopsys ZeBu emulation platforms.
- Support RTL bring-up, compilation, mapping, execution, and debug on emulation platforms.
- Develop and integrate testbenches, transactors, interfaces, and emulation models.
- Debug RTL and system-level issues using emulation and simulation methodologies.
- Collaborate with RTL, Design Verification, Architecture, Firmware, and SoC teams.
- Analyze emulation failures and improve test execution and debug efficiency.




- Support pre-silicon validation and software/firmware execution on emulated designs.

Qualifications
- 6+ years of experience in SoC/ASIC verification, hardware emulation, or pre-silicon validation.
- Hands-on experience with at least one of the following is mandatory:
- Cadence Palladium
- Synopsys ZeBu
- Strong understanding of RTL, Verilog/SystemVerilog , and SoC verification flows.
- Experience with emulation bring-up, compilation, debugging, and test execution.
- Good understanding of UVM, simulation, and pre-silicon verification methodologies.
- Scripting/programming experience in Python, Tcl, Shell, C/C++ , or similar is preferred.
- Robust debugging and problem-solving skills.
- Notice period of 0–30 days preferred.
- Candidates available to work from Bengaluru in a hybrid setup.

📌 Senior Emulation Engineer | 6+ yrs (Bengaluru)
🏢 leadIC Design
📍 Bengaluru