Job details:

Job Title: Digital RTL Design Engineer

Location: On-Site

Experience Level: Mid-Senior (3-7 years)

: Responsibilities:

Design and implement digital RTL for complex systems.

Collaborate with verification engineers to ensure design meets all functional and performance requirements.

Perform synthesis, timing analysis, and optimization to meet design specifications.

Debug and resolve design issues, ensuring high-quality and reliable designs.

Participate in design reviews and provide constructive feedback.

Document design processes, specifications, and methodologies.

Work closely with cross-functional teams (DFT, PD, DV) for integration and sign-off.

Requirements:

Bachelors or Master’s degree in Electrical Engineering.





Minimum of 4-7 years of experience in digital RTL design.

Proficiency in Verilog, and System Verilog.

Experience with industry-standard design tools such as Cadence, Synopsys.

Robust understanding of digital design principles and RTL coding.

Excellent problem-solving and debugging skills.

Experience in clock domain crossing (CDC) and reset domain crossing (RDC).

Knowledge of scripting languages (e.g., Python, Perl) is a plus.

Preferred Qualifications:

Experience with low-power design techniques.

Familiarity with protocols like LP/DDR, AXI, APB, AHB is desirable.

📌 Rtl Design Engineer (Bengaluru)
🏢 Acesoft Labs
📍 Bengaluru