- Job Title: RTL Design Engineer (IP Integration)
- Location: Hyderabad
- Experience: 4–7 Years
- Shift: Regular
- Education: B.E/B.Tech/M.Tech in Electronics, VLSI, or related fieldRole

Overview

- We are seeking an experienced RTL Design Engineer to join our SoC team in Hyderabad. In this role, you will contribute to RTL coding, IP integration, and design validation for next‑generation chiplet designs. You will gain hands‑on exposure to industry‑standard tools and methodologies while collaborating with highly skilled engineers across design, verification, and physical design teams.

- Key Responsibilities:
- Write and maintain RTL code in Verilog/SystemVerilog
- Support design integration, lint, CDC, RDC, VCLP, and synthesis checks
- Debug and resolve design issues efficiently
- Collaborate with cross‑functional teams to ensure smooth project execution
- Required Skills:




- Strong knowledge of IP integration
- Expertise in RTL Quality Checks (Lint, CDC, RDC, VCLP)
- Solid understanding of cross‑functional dependencies
- Proficiency in Verilog/SystemVerilog
- Solid grasp of digital logic design, FSMs, and timing concepts
- Exposure to synthesis, STA basics, and RTL methodologies
- Familiarity with EDA tools and scripting
- Excellent problem‑solving and debugging skills
- Good to HavePrior experience with AMD design flows
- Knowledge of low‑power design techniques, clocking, and resets
- Soft SkillsStrong verbal and written communication skills
- Ability to prioritize tasks and manage multiple deliverables in a fast‑paced environment

📌 RTL Engineer (Hyderabad)
🏢 QTIMINDS
📍 Hyderabad