19 Sep
|
Acesoft Labs
|
Hyderabad
19 Sep
Acesoft Labs
Hyderabad
- Experience on RTL2GDS Implementation i.e. Synthesis, Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.
- Should have experience on Physical Design Methodologies and lower tech nodes like 7nm, 6nm & 5nm.
- Should have experience in handling high frequency partitions & memory dominated designs.
- Should have experience on programming in Tcl/Tk/Perl.
- Well versed with timing constraints, STA and timing closure.
- Should have worked on minimum 3 tapeouts.
- Should have hands-on experience on Hierarchical level PV & signoff closure
- Tools: Innovus, Tempus
- Experience Range : 5 - 15 years
- Primary Skills : Physical Design, CTS, STA & Physical Verification.
📌 Physical Design Engineer (Hyderabad)
🏢 Acesoft Labs
📍 Hyderabad