Job DescriptionRequisition- SoC DFT Lead

NExperience-10+ Years

nLocation- Bangalore

N

n
- Tessent based SSNinsertion at block or Top level
N
- SSN validation
n
- SSN insertion expertise
N
- Tessent MBIST insertion
N
- Responsible for Implementing and integrating scan insertion, scan compression, MBIST, OCC and boundary scan at gate/RTL level.
N
- Team Handling Skill is preferred.
N

nKey Responsibilities

NSoC DFT Architecture & Leadership

NOwn SoC-level DFT architecture and strategy for custom and platform-based

NSoCs.

nDefine anddrive DFT implementation plans across multiple concurrent SoC

Nprograms.

nAct asthe technical authority and signoff owner for all DFT-related decisions and

Ndeliverables.

nExecution & Technical Ownership

NLead DFT RTL integration, scan insertion, and test architecture implementation.

NOwn and drive:

NScan, Compression, and ATPG strategy

NMBIST, BISR, and redundancy implementation

NJTAG / TAP, Boundary Scan, and debug infrastructure

NEnsure DFT readiness across functional, scan, and low-power modes.

NCollaborate with RTL, STA, and PD teams to ensure DFT-friendly design and

Nimplementation.

nDrive ATPG pattern generation, simulation, and debug to ensure high test

Ncoverage and quality.

nCross-Functional & Manufacturing Interface

NWork closely with physical design teams to ensure scan and test logic closure

Nwith minimal PPA impact.

NInterface with manufacturing, ATE, and OSAT teams on test requirements, vector

Ndelivery, and silicon bring-up.





NSupport post-silicon debug, yield ramp, and test optimization.

NRepresent in customer-facing technical discussions related to DFT

Nstrategy and signoff.

nMethodology & Team Development

NDefine and standardize DFT methodologies, flows, and checklists across

Nprograms.

nDrive automation, scripting, and reuse to improve DFT efficiency and

Npredictability.

nMentor and develop DFT engineers and leads, building deep technical and

Nexecution capability.

nReview and approve DFT signoff reports and tapeout readiness criteria.

NQualifications

nB.E./B.Tech or M.E./M.Tech in Electrical / Electronics / VLSI Engineering.

N12+ years of experience in DFT architecture and implementation for complex

NSoCs.

nProven track record of leading DFT implementation and signoff on multiple

Ncustom SoC tapeouts.

nStrong expertise in:

NScan, Compression, and ATPG methodologies

NMBIST, BISR, and memory repair schemes

NJTAG / TAP and Boundary Scan

NDFT RTL integration and pattern simulation

NHands-on experience withindustry-standard DFT tools, such as:

NSiemens Tessent

nSynopsys DFTMAX / TestMAX

NSpyGlass DFT (or equivalent)

NStrong understanding of:

NLow-power DFT challenges(UPF/CPF)

NScan and test-mode timing closure

NPhysical implementation constraints for DFT

NExperience working with manufacturing, ATE, and post-silicon validation teams.

NExcellent problem-solving, communication, and leadership skills.

📌 Lead Engineer (Bengaluru)
🏢 Angel and Genie
📍 Bengaluru