About the Role

We are looking for an experienced Design Verification Engineer to join our team on a part-time remote basis . The ideal candidate should have strong hands-on expertise in SystemVerilog, UVM, AMBA protocols, functional verification, coverage closure, and simulation/debugging .

Key Responsibilities

• Develop and maintain SystemVerilog/UVM-based verification environments for IP, subsystem, and SoC-level designs

• Understand design specifications and develop comprehensive verification test plans

• Develop directed and constrained-random testcases

• Perform functional and code coverage analysis and drive coverage closure

- Debug simulation failures and collaborate with RTL designers to resolve issues
- Execute regression suites, analyze failures, and improve verification efficiency

• Work with AMBA protocols and verify protocol-level functionality

• Integrate and execute power-aware simulations and low-power verification

• Work with UPF/CPF for low-power design verification

• Collaborate with RTL, DFT, Physical Design, and post-silicon validation teams

- Document verification environments, test plans, test results,



and coverage status

Required Skills

✅ Strong SystemVerilog experience

✅ Hands-on UVM expertise

✅ Strong debugging and simulation skills

✅ Good understanding of AMBA protocols

✅ Experience in functional and code coverage

✅ Experience with constrained-random verification

✅ IP / Subsystem / SoC verification experience

✅ Experience with regression execution and failure analysis

✅ Knowledge of UPF/CPF and low-power verification is preferred

✅ Good collaboration and documentation skills

What We Offer

? Part-Time Remote Opportunity

? Flexible engagement model

? Prospect to work on complex semiconductor verification projects

? Exposure to IP/SoC-level verification and advanced verification methodologies

? Interested candidates can apply through LinkedIn with their updated profile.

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📌 Freelance Design Verification Engineer (India)
🏢 IndiTech Consulting
📍 India