Hiring for DFT Senior Engineer 9+ years

nLooking for an experienced DFT Engineer with 9+ years of industry experience in ASIC/SoC Design for Test (DFT) implementation and validation. The candidate will be responsible for architecting, implementing, and verifying DFT solutions for complex SoCs.

nKey Responsibilities

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- Define and implement DFT architecture for complex SoCs.
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- Integrate and verify Scan, MBIST, Boundary Scan (JTAG), and compression logic.
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- Perform DFT rule checks, ATPG pattern generation, and pattern validation.
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- Analyze test coverage, debug coverage issues, and drive closure.
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- Develop and maintain DFT flows, scripts, and automation.
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- Support post-silicon bring-up and production testing activities.
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- Work closely with RTL, Verification, Physical Design, and Product Engineering teams.
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- Ensure successful DFT sign-off and tape-out readiness.
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nMandatory Skills

n9+ years of hands-on DFT experience





nStrong expertise in:

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- Scan Insertion and Scan Compression
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- ATPG and Fault Coverage Analysis
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- MBIST Implementation and Verification
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- JTAG / IEEE 1149.1
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- DFT DRC and Debug
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- SoC-level DFT Integration
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nEducational Qualification

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- B.E./B.Tech/M.E./M.Tech in Electronics, Electrical, VLSI, or related disciplines.
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nNotice period : Any

nLocation: Open to discuss

nInterested candidates can share their updated resume along with the following details:

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- Name
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- Contact
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- Email id
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- Current Company
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- Total Experience
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- Relevant DFT Experience
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- Current CTC
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- Expected CTC
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- Notice Period / LWD
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- Current Location
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- Preferred Location
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nEmail: [email protected]

📌 DFT Senior Engineer (Bengaluru)
🏢 HCLTech
📍 Bengaluru