Analog / Custom Layout Design Engineer (TSMC 3nm | FinFET | Cadence | Calibre)

Experience: 4 to 8 Years

Location: Hyderabad

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We are seeking a highly skilled Analog / Custom Layout Design Engineer to drive the design and development of critical analog, mixed-signal, and custom digital layouts, supporting full-chip level integration in advanced FinFET process technologies.

You will be responsible for end-to-end layout execution from schematic translation and floor planning to verification and final sign-off — while collaborating closely with circuit designers, verification engineers, and project leads.

Key Responsibilities:

- Design, develop, and implement analog, mixed-signal, and custom digital layouts for complex SoC and ASIC designs.
- Perform layout verification including LVS, DRC, Antenna checks, and ensure compliance with foundry rules (TSMC 3nm/5nm/7nm/16nm).
- Execute and review block-level and full-chip layout integration, ensuring timing, reliability, and manufacturability targets are met.
- Utilize Cadence Virtuoso (VLE/VXL) and Mentor Calibre DRC/LVS tools to achieve design accuracy and productivity.
- Conduct design quality checks, documentation, and maintain design version control.
- Mentor and guide junior layout engineers — review their work, provide feedback, and ensure project delivery quality.
- Collaborate with circuit design, physical verification, and integration teams to resolve issues and streamline sign-off.
- Contribute to project management,



ensuring on-time delivery and alignment with tape-out schedules.
- Suggest innovative layout methodologies and challenge traditional approaches to improve design efficiency and performance.

Required Skills & Qualifications:

- 4–8 years of experience in Analog/Custom Layout Design within advanced CMOS and FinFET technologies.
- Hands-on experience with TSMC 3nm process is mandatory (TSMC certification preferred).
- Strong expertise in Cadence Virtuoso (VLE/VXL) and Mentor Calibre DRC/LVS.
- Proficiency in layout verification, Antenna check, LVS/DRC debugging, and documentation.
- Good understanding of analog layout techniques — matching, shielding, common-centroid structures, ESD, latch-up prevention, and guard rings.
- Robust problem-solving skills and a clear understanding of layout fundamentals and physical verification principles.
- Proven ability to work independently with minimal supervision and meet tight deadlines without compromising quality.
- Excellent communication, teamwork, and mentoring abilities.

Preferred Qualifications:

- Exposure to multi-project environment and cross-site collaboration.
- Experience in custom layout automation or layout scripting (Skill / Python / Perl).
- Familiarity with FinFET process challenges (3nm/5nm/7nm) — EMIR, reliability, and density trade-offs.
- Knowledge of full-chip integration and top-level verification flows.

📌 Custom Layout Engineer (Hyderabad)
🏢 Acesoft Labs
📍 Hyderabad