Description

- Good knowledge of Basic Analog/Digital concepts.
- Good knowledge of Verilog/SV concepts.
- Experience in using spice simulation and digital simulation tools like Virtuoso, primesim, Finseim, Hspice, Xcellium, Simvision, Waveview.
- Experience in understanding Spice simulation environment/Digital simulation environment, able to debug analog/digital design related issues.
- Work experience in co-sim simulation designs is a plus.
- Positive scripting skills using perl, python is a plus.

• Must possess good communication skills and ability to work well in a team.

Bachelors with 2+ years of work experience or Post Graduate Degree in Electronics Engineering or related engineering field with 1-2 years of working experience is required. We recruit, hire, train, promote, discipline,



and provide other conditions of employment without regard to a person's race, color, religion, sex, age, national origin, disability, sexual orientation, gender identity and expression, pregnancy, veterans status, or other classifications protected under law.

This includes providing reasonable accommodation for team members' disabilities or religious beliefs and practices.

Each manager, supervisor and team member are responsible for carrying out this policy. The EEO Administrator in Human Resources is responsible for administration of this policy. The administrator will monitor compliance and is available to answer any questions on EEO matters.

📌 analog verification (Hyderabad)
🏢 Acesoft Labs
📍 Hyderabad