Role & responsibilities
Description
- 4 to 8 years of experience in Design and development of critical analog, mixed-signal, custom digital block.
- TSMC 16/12nm,7nm,5nm,3nm and below (foundries are also fine like Intel, Samsung, GF)
- Preferably TSMC 5nm/3nm experience.
- Responsible full chip level integration support.
- Verification flows - LVS/DRC/DFM/Antenna check/EMIR experience.
- Responsible for on-time delivery of block-level layouts of acceptable quality.
- Expertise in Cadence VLE/VXL and Mentor Graphic Caliber DRC/LVS is a must.
- Analog blocks like Regulators/Charge pumps/Power Management etc..
- HBM experience is an added advantage.
PLs share resumes/CV to
[email protected]
Preferred candidate profile
- BE or MTech in Electronics/VLSI Engineering
- Good communications skills as we work with cross-functional teams.
- Positive hands-on experience in recent times on lowers nodes.
- Should work independently
📌 Analog Layout Engineer | Physical Design Engineer | AMS Layout Design (Bengaluru)
🏢 Acesoft Labs
📍 Bengaluru