Job DescriptionWe are looking for an experienced Senior ASIC RTL Design Engineer to join our growing semiconductor design team. The ideal candidate will have robust experience in RTL development, micro-architecture design, and SoC integration.
NLocation: Bangalore/Hyderabad
NExperience: 8–15 Years
NKey Responsibilities:
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Design and develop synthesizable RTL using Verilog/System Verilog N
Translate architecture specifications into micro-architecture and RTL implementation N
Develop high-performance and low-power digital design blocks N
Work closely with verification teams for functional validation and debug N
Perform design reviews and ensure coding quality and design guidelines N
Collaborate with physical design teams to meet timing, power, and area requirements N
Debug RTL issues and support silicon bring-up when required N
nRequired Skills:
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Solid expertise in Verilog and System Verilog N
Solid understanding of digital design fundamentals and computer architecture N
Experience with AMBA protocols such as AXI, AHB,
and APB N
Knowledge of synthesis,timing closure, and low-power design techniques N
Familiarity with simulation and debugging tools N
Experience working in ASIC/SoC design environments N
nPreferred Qualifications:
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Solid debugging and problem-solving skills N
Bachelor's or master's degree in electrical engineering, Computer Engineering, or a related field. N
Solid understanding ofdigital logic design principles. N
nAbout us:
NTessolve Semiconductors, a venture of Hero Electronix, is a Design and Test Engineering Service Company providing End to End Solutions from Product Engineering, Software, Hardware, Wireless, Automotive and Embedded Solutions. Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, spec to the product.
NWith 2500+ employees worldwide, Tessolve provides a one-st