Job Summary

Lead RTL and microarchitecture development for UALink-based IP/subsystems, focusing on high-bandwidth, low-latency data movement and scalable interconnect design.

Key Responsibilities
Lead UALink IP/subsystem RTL development.
Translate protocol requirements into detailed microarchitecture.
Design high-performance control and data-path logic.
Work on buffering, arbitration, flow control, ordering, and error handling.
Develop and review SystemVerilog RTL.
Drive performance, area, power, and latency optimization.
Collaborate with verification, SoC integration, and physical design teams.
Debug complex functional and integration issues.
Review RTL and mentor engineers.
Support silicon debug and issue resolution.

Required Skills
Solid RTL and microarchitecture experience.
Experience with high-speed interconnects.




Solid understanding of data movement, flow control, arbitration, and buffering.
Excellent SystemVerilog/Verilog skills.
Experience with CDC, lint, synthesis, and timing.
Robust debugging and technical leadership skills.

Preferred
Direct UALink experience.
Experience with PCIe, CXL, CHI, CCIX, Ethernet, or similar technologies.
Experience with AI/accelerator or high-performance compute SoCs.

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Lead Logic Design For Ualink Ip/subsystem Engineer Bengaluru
🏢 Astera Labs
📍 Bengaluru