Gate-Level Simulation EngineerLocation: Hyderabad

Workplace: Hybrid

Employment Type: Full time

Experience: 2+ years

Notice Period:candidates with 0–30 days notice period will be given priority.

We are looking for a hands-on Gate-Level Simulation Engineer with 2+ years of relevant industry experience in GLS and pre-silicon verification. The ideal candidate should have strong practical experience debugging gate-level simulations and working with netlists, SDF, timing, and RTL-to-gate flows.

Key Responsibilities
Perform Gate-Level Simulation (GLS) using post-synthesis and/or post-layout netlists.
Debug functional mismatches between RTL and gate-level simulations.
Analyze issues related to SDF back-annotation, timing, X-propagation, resets, clocks, and initialization.
Execute and debug simulation testcases and regressions.
Analyze simulation logs and waveforms to identify root causes of failures.
Collaborate with RTL, Design, STA, Synthesis, and Verification teams to resolve issues.
Support pre-silicon verification and signoff activities.
Automate simulation and debugging workflows using scripting where applicable.

Required Skills




2+ years of hands-on experience in Gate-Level Simulation (GLS).
Solid understanding of RTL-to-gate flow, synthesis, netlists, and SDF.
Experience with zero-delay and/or SDF-based GLS.
Strong debugging skills using logs and waveform viewers.
Good proficiency in Verilog/SystemVerilog.
Experience with simulators such as VCS, Xcelium, or Questa.
Good understanding of digital design and verification concepts.
Working knowledge of Linux/Unix and scripting using Shell, Python, or Perl.

Preferred Skills
Experience debugging X-propagation, timing, reset, and clock-related GLS issues.
Exposure to STA reports and timing constraints.
Experience with SoC/IP-level verification or semiconductor product development.
Solid ability to independently root-cause simulation failures.

Qualification
Bachelor's/Master's degree in Electrical/Electronics Engineering, VLSI, or a related field.

Notice PeriodImmediate Joiners will be given first priority.

Candidates with a 0–30 days notice period are strongly preferred.

📌 Gate Level Simulation Engineer 2+ Yrs Hyderabad (India)
🏢 Leadic Design
📍 India