Key Skills: Architecture, C++, Design, EDA, ETL, Go, Security, SoC, SystemVerilog

Roles & Responsibilities:
Collaborate closely with RTL designers and architects to understand specifications and microarchitecture details.
Develop current verification environments and enhance existing environments, including stimulus generation, checking, and coverage infrastructure.
Create and execute verification plans and test plans.
Implement verification strategies in partnership with other verification engineers.
Drive functional and code coverage closure.
Debug and resolve complex design and verification issues.
Contribute to continuous improvement of verification methodologies, infrastructure, and best practices.
Provide technical guidance and support to less experienced engineers.

Skills Required:
5+ years of experience in IP, subsystem, or SoC verification.
Strong proficiency in SystemVerilog and Verilog.
Experience with UVM or other industry-standard verification methodologies.




Experience developing constrained-random verification settings and reusable verification components.
Experience creating verification plans and test plans.
Understanding of SoC verification, including software-driven verification flows.
Experience with scripting languages such as Python, Perl, or similar.
Strong debugging, analytical, and problem-solving skills.
Robust interpersonal and communication skills, with the ability to collaborate effectively across geographically distributed teams.

Nice To Have
Experience with Arm-based designs and/or Arm system architectures.
Experience with AMBA protocols such as CHI, AXI, AHB, and APB.
Experience with JTAG, SWD, or TAP-based debug infrastructures.
Experience with clock domain crossing (CDC), reset domain crossing (RDC), and power-aware verification.
Exposure to low-power design techniques and UPF/CPF methodologies.
Experience with DFT concepts, including scan and MBIST.

Education: Bachelor's degree in Engineering

📌 Senior Verification Engineer Bengaluru
🏢 MyCareernet
📍 Bengaluru