Job Summary

Responsible for end-to-end development, integration, and enablement of PDKs supporting design, verification, and signoff across technology nodes.

Drives component development (PCells, techfiles, rule decks) while ensuring scalability, quality, and compliance with foundry requirements.

Key Responsibilities

- Develop and integrate PDK components: devices, PCells, rule decks, technology files, and configurations.
- Execute development tasks with increasing independence and ownership across modules and nodes.
- Debug, validate, and ensure quality and consistency of PDK deliverables.
- Collaborate with design, QA, CAD, and customers for issue resolution and alignment.
- Build and scale automation frameworks for PDK generation, validation, and regression.
- Drive methodology improvements, coding standards, and reusable architectures.
- Lead multi-node development strategies (legacy advanced nodes).
- Manage end-to-end delivery: planning, tracking, risk mitigation, and execution.
- Mentor teams and build technical capability across functions.
- Define organization-level development strategy, roadmap, and transformation initiatives.
- Drive AI adoption for debugging, productivity, and predictive development workflows.

Required Skills

- Strong understanding of PDK architecture, device physics, and layout concepts.
- Expertise in PDK components development (PCells, rule decks, techfiles).
- Proficiency in EDA tools (Cadence/Synopsys environments).
- Programming skills: SKILL, Python, Shell, Tcl/Perl.
- Solid debugging, problem-solving,



and cross-domain integration skills.
- Experience in automation, scalable system design, and methodology definition.
- Ability to lead teams, drive delivery, and manage customer communication.

Tools

- Cadence Virtuoso, Synopsys Custom Compiler.
- PCells/PyCells, Techfiles, Rule decks (DRC/LVS/DFM).
- Calibre, ICV, Pegasus, PVS.
- SKILL, Python, Shell, Tcl/Perl.
- Git, CI/CD pipelines.
- AI-assisted debugging and automation tools.

Qualifications

- B.E./B.Tech/M.E./M.Tech in Electronics / Electrical / VLSI / Semiconductor or related field.
- 3 to 10 years of experience in PDK development, design enablement, or EDA flows.

Nice to Have

- Multi-node PDK development (advanced nodes, FinFET).
- Cross-foundry PDK enablement experience.
- Automation frameworks for PDK generation/validation.
- AI/ML-driven debug and development workflows.

Additional Key Responsibilities

1. To leverage design expertise to ensure that software and products exhibit user-friendliness, intuitiveness, and alignment with user expectations, contributing to the creation of seamless user experiences.
2. To lead a team of designers, provide guidance, and ensure the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends and emerging technologies to drive innovation and excellence in design.

Skill Requirements

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Other Requirements

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📌 Senior Design Lead (India)
🏢 HCL Technologies
📍 India