Job Description

Job Summary

We are looking for an experienced Lead DFT Engineer to drive Design-for-Test implementation, verification, and sign-off for complex SoCs and IPs.

The ideal candidate should have strong hands-on expertise in Scan Insertion, MBIST, ATPG, DFT architecture, and coverage optimization, along with experience using industry-standard DFT tools.

Key Responsibilities

- Define and implement DFT architecture for complex SoCs and IPs.
- Drive scan insertion, scan compression, scan stitching, and scan verification.
- Implement and integrate MBIST solutions for embedded memories.
- Develop and optimize ATPG patterns for stuck-at, transition, and advanced fault models.
- Perform DFT verification, fault simulation, coverage analysis, and pattern validation.
- Debug DFT issues at RTL and gate-level.
- Collaborate with RTL, Physical Design, STA, and Test Engineering teams.
- Drive DFT closure and sign-off activities.
- Develop automation scripts using TCL, Python, or Perl.





Required Skills

- 812 years of hands-on DFT experience.
- Strong expertise in Scan Insertion and Scan Compression.
- Hands-on experience with MBIST implementation and verification.
- Robust knowledge of ATPG generation and fault simulation.
- Experience with Siemens Tessent, Synopsys TestMAX, DFT Compiler, or equivalent.
- Knowledge of JTAG / IEEE 1149.1, boundary scan, and IEEE 1500.
- Experience with gate-level simulation, DFT validation, and scan debug.
- Proficiency in TCL, Python, or Perl scripting.
- Strong analytical and debugging skills.

Educational Qualification
B.E. / B.Tech / M.E. / M.Tech in Electronics, Electrical Engineering, Computer Science, or a related field.

Job Location: Bangalore
Experience: 812 Years
Notice Period: Immediate to 90 Days

📌 Lead DFT Engineer Scan 8 To 12 Years (Bengaluru)
🏢 Kairos Technologies
📍 Bengaluru