Qualification: B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI or related disciplinesWhat You’ll Be Working On:• Block-level and full-chip Static Timing Analysis• Development, validation and debugging of SDC constraints• Setup, Hold, Recovery & Removal analysis• MCMM timing analysis across PVT corners• Timing closure across multiple design scenarios• Root-cause analysis and resolution of timing violations• Clock timing and clock architecture analysis• Timing ECOs and implementation changes• Timing sign-off and generation/review of timing reports• OCV / AOCV / POCV and derating analysis• Signal Integrity / Crosstalk-aware timing analysis• Timing closure for high-performance and complex SoC/ASIC designsWhat We’re Looking For6+ years of hands-on STA experienceStrong expertise in Synopsys PrimeTime and/or Cadence TempusExcellent understanding of STA concepts and timing methodologiesStrong experience with SDC constraintsGood understanding of MCMM, OCV, AOCV & POCVStrong knowledge of clock architecture, clock timing and clock-related issuesExperience with timing ECOs and timing closure methodologiesGood understanding of the ASIC Physical Design flowStrong Tcl scripting skillsPython scripting knowledge will be an added advantageGood to Have• Full-chip STA and sign-off experience• Experience with advanced technology nodes• Exposure to Signal Integrity / Crosstalk analysis• Experience with low-power designs• Experience working on large and complex SoC designs

📌 STA Lead (Vasanth Nagar)
🏢 leadIC Design
📍 Vasanth Nagar