Job Title: VLSI Verification Engineer

Experience: 1 to 3 years

Location: Hyderabad

:

We are seeking a highly motivated VLSI Verification Engineer with hands-on experience in circuit simulation, gate-level verification, and schematic analysis. The candidate will work on SPICE-based simulations, GLS with SDF back annotation, and transistor-level debugging to ensure design quality and sign-off readiness.

Key Responsibilities:
Develop, understand, and analyze block-level & memory schematics.
Perform SPICE simulations (DC, transient) and correlate with gate-level models.
Conduct gate-level simulations with SDF back annotation.
Debug annotation issues, timing violations, and GLS failures.
Work on latch-based designs and timing requirements.
Perform schematic-to-behavior correlation and what-if analysis.
Write and use SystemVerilog Assertions to capture expected behavior.




Collaborate with design/verification teams to root-cause and fix failures.

Mandatory Skills:
SPICE circuit simulation (HSPICE/Spectre/NGSpice or equivalent)
Gate-level simulation (GLS) with SDF annotation
Verilog MOS switch-level models, netlist simulations
Debugging at transistor and gate-level
Static Timing Analysis fundamentals (timing libraries, timing arcs, latch-based designs)

Valuable to Have:
Knowledge of SystemVerilog Assertions (SVA)
Familiarity with UVM methodology
Prior experience with memory designs

Desired Candidate Profile:
1 to 3 years of relevant VLSI verification/circuit simulation experience
Robust analytical and debugging skills
Valuable communication skills to interact with design peers and cross-functional teams

📌 Design And Verification Engineer Hyderabad (India)
🏢 Acesoft Labs
📍 India