Position: Design Verification Engineer

Location: Bangalore

Experience: 4+ Years

Budget: 1618 LPA

Joining Availability: Immediate / Within 1 Month

Position Overview

Green Semiconductors Pvt. Ltd. is looking for an experienced Design Verification Engineer with strong hands-on expertise in SystemVerilog, UVM methodology, AMBA protocols, regression debugging, and functional coverage closure.

The candidate will be responsible for developing and enhancing verification environments, executing regressions, debugging failures, and driving functional coverage to closure.

Key Responsibilities
Develop, maintain, and enhance UVM-based verification testbenches.
Develop reusable verification components, sequences, test cases, and coverage models.
Execute and debug functional and regression simulations.
Analyse regression failures and perform root-cause debugging.
Drive functional and code coverage closure.
Develop and update verification test plans based on design specifications.
Perform protocol-level verification and debugging for AMBA protocols.
Work closely with RTL/design teams to identify, analyse, and resolve functional issues.
Maintain and update verification environments and testbench components.
Track verification progress, bugs,



regression status, and coverage metrics.

Mandatory Technical Skills
SystemVerilog
UVM Universal Verification Methodology
AMBA protocols AXI/AHB/APB
UVM testbench development and enhancement
Regression execution and debugging
Functional/code coverage analysis and closure
Strong debugging and problem-solving skills

Tools / Simulation Environment Hands-on experience with industry-standard simulation and debugging infrastructure, particularly:
Synopsys (SNPS) simulation tools
Cadence (CDNS) simulation tools

Preferred Skills
Previous experience in the Image Processing / Imaging domain
Robust understanding of ASIC/SoC verification methodology
Experience working in IP-level or SoC-level verification environments

Candidate Profile
4+ years of relevant Design Verification experience
Robust hands-on experience rather than only theoretical knowledge of UVM
Ability to independently handle testbench updates, regression execution, debugging, and coverage closure
Positive analytical, debugging, communication, and documentation skills
Candidates who can join immediately or within 1 month will be preferred.

📌 Design And Verification Engineer Bengaluru
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📍 Bengaluru