Role & responsibilities:
Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs.
Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.
Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
Co-work with international colleagues on developing recent verification flows to take on the challenges in DRAM and emerging memory design.
Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.

Core Requirements
Basic understanding of CMOS and gate level circuit designs.




Familiarity with SPICE
Familiarity with Verilog simulations
Positive communication skills and ability to work well in a team

Preferred Qualities
Analytical capability for complex gate level circuit designs.
Experience in SystemVerilog, PLI coding
Experience in UVM Test Bench
Experience in DRAM, SRAM or other memory related fields
Experience in AMS verification and co-sim

Education Bachelors or Post Graduate Degree in Electronics Engineering or related engineering field required

📌 Memory Circuit Design Verification Engineer Hyderabad
🏢 Acesoft Labs
📍 Hyderabad