Roles & Responsibilities:
To be part of a highly skilled ASIC Team working on the newest technology nodes
Responsible for overall IP/Block and sub-system verification from test plan creation, SystemVerilog/ UVM testbench development to signoff
Ensure first pass product through multi-dimensional verification coverage including mixed mode verification
Mentoring and coaching junior team members
Pair with similar domain specialists across other geographical locations on core technical initiatives

Skills required:
Should have expertise in IP/Block/Subsystem level verification and AMBA protocols-APB/AHB/AXI.
Proven track record of building test plan, UVM Setting and test benches
Experience with RTL debugging, scoreboard, assertions, functional coverage coding and code coverage analysis




Sound knowledge of Verilog and System Verilog languages
The position requires valuable written & verbal communication skills as well a solid commitment and ability to work in cross functional and globally dispersed teams.

Educational Qualification
M.S./M.Tech, BS/BE (Electronics)
Experience Required : 3+ Years

Mandatory Skills:
Should have working experience on AXI/AHB protocols.
Should have working experience on IP/Block/Subsystem Verification starting from verification plan to sign off of the IP.
Should be expert in System Verilog and UVM methodology.

Domain
IP/Block / Subsystem Verification (RTL Front end verification).

📌 Rtl Front End Verification, Ip Verification Engineer Hyderabad
🏢 Acesoft Labs
📍 Hyderabad