Experience: 8 to 10yrs

Minimum qualifications
Bachelor’s degree in electrical engineering or computer science
Verilog/SystemVerilog based verification experience at Subsystem and Full chip level.

Preferred qualifications
Bachelor’s degree in electrical engineering or computer science with 10+ years of relevant experience, or master’s degree in electrical engineering or computer science with 10 years of relevant experience.
Experience with digital system based on AMBA Bus protocols like ACE/AXI/AHB/APB and high-speed interface protocols like Pcie, ethernet, DDR
Experience with System Verilog Assertions with industry standard tools a plus
Experience with SOC boot flow, clocking and platform bring up in Emulators or Silicon desired
Experience with Low Power Verification and power management flows.
Experience with RTL, GLS level simulations




Knowledge and Experience working on PCIE/Ethernet and other HSIO desired
Experience in UVM/OVM based Methodology Development.
Experience in coverage report generation & integrating in different verification environments into one common platform.

Roles & Responsibilities:
Be part of a team to verify complex systems on chip designs. Interact with design engineers to identify key verification scenarios.
Create and enhance constrained-random verification settings using UVM/ System Verilog
Create complex C/SV tests using reusable test libs.
Team player and a mentor who is self-driven, motivated and guides a team of junior engineers
Responsible for quality and timeliness of the team output

📌 Sr Soc Design Verification Engineer Bengaluru
🏢 Mettlesemi Systems and Technologies Private
📍 Bengaluru