Job DescriptionJob Title: Lead DFT Engineer
NExperience: 7+ Years
NLocation: Bangalore
NEmployment Type: Full time
NIndustry: Semiconductors / ASIC / SoC Design
NJob Summary:
NWe are looking for a LeadDFT Engineer to drive DFT architecture, planning, and implementation across complex SoC/ASIC designs. As a technical leader, you will mentor junior engineers, collaborate with cross-functional teams, and ensure world-class testability and manufacturability of silicon products.
NKey Responsibilities:
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Define and drive DFT strategy and architecture for multiple ASIC/SoC projects. N
Lead implementation andverification of DFT features like: N
Scan insertion and compression (e.G., EDT) N
ATPG pattern generationand fault grading N
MBIST and Logic BIST insertion and validation N
Boundary scan (IEEE 1149.1/1149.6), IJTAG (1687) N
Manage end-to-end DFT flow — from RTL to gate-level netlist and silicon bring-up. N
Collaborate with RTL, STA, PD, and test engineering teams for seamless integration. N
Perform pattern generation,



fault simulation, and debug test coverage gaps. N
Own DFT signoff, timingclosure (DFT-related paths), and ATE pattern delivery. N
Support silicon bring-up, test vector validation on ATE, and yield optimization. N
Mentor and guide juniorDFT engineers;
conduct design reviews and training sessions. N
Develop and maintain DFT automation scripts and infrastructure. N

nRequired Skills and Experience:
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B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Design. N
7+ years of experience in DFT for complex ASIC or SoC designs. N
Expertise in scan insertion, compression, ATPG, MBIST, and boundary scan. N
Hands-on experience with DFT tools such as: N
Synopsys: DFT Compiler, TetraMAX, TestMAX N
Siemens EDA: Tessent ScanPro, MBIST, IJTAG N
Cadence/others: Modus, Encounter Test N
Solid knowledge of RTLdesign, STA, and synthesis flows. N
Proficient in scriptinglang

📌 Lead Dft Engineer Karnataka
🏢 ACL Digital
📍 Karnataka