Job DescriptionSRAM Memory Layout Engineer

NExperience: 3–6 Years

NLocation: Bangalore

NNotice Period: Immediate to 60 Days

NTechnology: TSMC 2nm/3nm | Samsung 2nm/4nm

NJob Description

nWe are looking for experienced SRAM Memory Layout Engineers with strong hands-on expertise in advanced-node memory layout and physical verification. The ideal candidate should have experience working on SRAM macros and memory structures from layout development through tape-out.

NKey Responsibilities & Skills

N

n
3–6 years of hands-on experience in SRAM Memory Layout.
N
Solid experience with Single Port, Dual Port, Pseudo Dual Port SRAM, Register File, FIFO, and Embedded Memory macros.
N
Hands-on experience with TSMC 2nm/3nm and/or Samsung 2nm/4nm technology nodes.
N
Develop and integrate bit-cell arrays, sense amplifiers, decoders, column muxes, row/column periphery, and top-level memory blocks.
N
Experience across the complete layout lifecycle, including floorplanning, placement, routing, optimization, DRC/LVS/ERC, PEX, and tape-out.
N




Strong knowledge of matching, symmetry, EM/IR, density, antenna, ESD, and advanced-node design rules.
N
Proficiency in Cadence Virtuoso and Calibre DRC/LVS/PEX.
N
Experience in area, performance, power, yield, and reliability optimization.
N
Robust debugging skillswith hands-on experience in PV issue resolution and ECO implementation.
N
Good scripting skills in Tcl/Python for layout automation and flow improvement will be an added advantage.
N
Ability to collaborate effectively with Memory Design, Circuit Design, and Verification teams.
N

nPreferred Candidate Profile

N

n
Strong understanding of advanced-node SRAM layout methodologies.
N
Good problem-solving and debugging skills.
N
Ability to independently handle layout tasks and resolve physical verification issues.
N
Robust communication and cross-functional collaboration skills.
N

📌 Hiring: Sram Memory Layout Engineer Karnataka (India)
🏢 Modernize Chip Solutions (MCS)
📍 India