Soc Interconnect And Fabric Rtl Designer (Yelahanka)

Soc Interconnect And Fabric Rtl Designer (Yelahanka)

21 Sep
|
Zyoin Group
|
Yelahanka

21 Sep

Zyoin Group

Yelahanka

About the job

We are looking for on-chip SoC Interconnect micro-architect and design lead for chiplet based high-performance Compute and AI silicon development.

What You’ll Do
- Define on-chip fabric topologies connecting the multiple subsystems
- Specify the data-path fabric for the high-bandwidth routes: bandwidth provisioning, pipeline depth, buffering strategy, and back-pressure propagation between major subsystems.
- Architect the register-access fabric with address decoding and access-protection logic.
- Define the arbitration and QoS policy for shared fabric resources: priority assignment per traffic class, bandwidth reservation, and starvation-prevention mechanisms.
- Own the fabric error-handling architecture: how illegal accesses, timeouts, and protocol violations are detected, logged, and reported to the management subsystem.
- Own the CDC strategy for every clock-domain boundary on the die and documenting the timing constraints for each.
- Own or closely review all fabric RTL: bus bridges, async FIFOs, arbiters, address decoders,



and pipeline registers that form the on-chip interconnect.
- Drive integration assembly: own the top-level connectivity netlist that instantiates all major blocks and wires them through the fabric, serving as the integration point of truth.
- Coordinate with subsystem leads align on interface protocols, handshake semantics, and reset sequencing at each fabric boundary.
- Define and own the fabric performance model: estimate bandwidth utilization per path under representative traffic mixes for each operating mode and identify bottlenecks.
- Establish fabric-level bring-up tests: register accessibility checks, path connectivity tests, and loopback sequences that confirm the interconnect is healthy before full subsystem integration testing begins.
- Coordinate with the physical design team on fabric floorplan implications: block placement driven by dominant data flow, clock-region boundaries, and wire-length budgets for timing cl

📌 Soc Interconnect And Fabric Rtl Designer (Yelahanka)
🏢 Zyoin Group
📍 Yelahanka

Reply to this offer

Impress this employer describing Your skills and abilities, fill out the form below and leave Your personal touch in the presentation letter.

Subscribe to this job alert:

Get the latest job offers by email for: soc interconnect and fabric rtl designer (yelahanka) / yelahanka

Subscribe to this job alert:

Get the latest job offers by email for: soc interconnect and fabric rtl designer (yelahanka) / yelahanka