Memory Layout Manager (Bengaluru)

Memory Layout Manager (Bengaluru)

21 Sep
|
Intel
|
Bengaluru

21 Sep

Intel

Bengaluru

Job Details:

Job Description:
The Role and Impact
We are seeking a skilled and motivated Layout Design Engineering Manager to lead a team of layout engineers in delivering best in class SRAM,RF,ROM,CAM Memory compiler designs across the Intel's bleeding FinFETs,GAA technologies. In this role, you will champion technical execution by overseeing compiler friendly and optimized floorplanning, high-density,performance based placement and routing template, and rigorous physical sign-off processes including DRC, LVS, Yield, DFM, Density, parasitic extraction, Noise Reliability i.e. EM, IR. You will provide technical guidance, set clear goals, and foster cross-functional collaboration with circuit design, Tilers, and foundry teams to meticulously optimize memory area, performance, power, and yield. Beyond daily execution, you will spearhead layout methodology innovations, establish advanced automation flows using SKILL, Python, or Tcl, and cultivate a culture of technical excellence by mentoring senior and staff-level engineers.



The role requires a robust vision for leveraging AI and ML technologies (such as reinforcement learning for routing or predictive analytics for DRC debugging) to make execution significantly more efficient, robust, and high-quality.

Business group
The Intel Foundry group plays a pivotal role in enabling innovative semiconductor manufacturing solutions that power Intel's products and those of our partners worldwide. As part of the BA Memories organization, this position supports the development of advanced memory technologies and methodologies, empowering Intel's mission to shape the future of technology and create world-changing advancements.

Key Responsibilities
- Lead and mentor a team of layout design engineers to developed world class memory compiler designs on FinFets/GAA technologies, ensuring alignment with organizational goals and timelines.
- Oversee the design, development, modification, analysis, and verification of memory compiler la

📌 Memory Layout Manager (Bengaluru)
🏢 Intel
📍 Bengaluru

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