Job Description
Location: Bengaluru
nExperience: 4–10 years
nEmployment Type: Full-time
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nAbout the Role
nWe are looking for SoC design engineers to own RTL integration and front-end signoff for complex SoCs. You will integrate IPs at subsystem and top level, and drive Lint, CDC, RDC, low-power (VCLP) and synthesis checks to closure for tapeout.
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nKey Responsibilities
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- SoC integration: Integrate IPs at subsystem and top level, including clock, reset, memory, pad/IO and interconnect. Build and maintain top-level RTL and connectivity.n
- Lint: Run Lint checks, analyze violations, drive fixes with IP owners, and manage waivers to signoff.n
- CDC/RDC: Set up constraints, and analyze synchronizers, reconvergence, glitches and reset domain crossings. Deliver clean signoff reports.n
- Low power (VCLP): Write and review UPF. Verify isolation, level shifters, retention and power switches using static low-power checks.n
- Synthesis: Write SDC constraints, run synthesis, and improve timing, area and power QoR. Run logic equivalence checks (RTL vs netlist).n




- Collaboration: Work with verification, DFT, STA and physical design teams through tapeout.n

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nMust-Have Skills
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- Strong Verilog/SystemVerilog RTL design and debug.n
- Hands-on experience with at least three of: Lint, CDC, RDC, VCLP/UPF, synthesis, SoC integration.n
- Positive understanding of clocking, reset architecture and low-power design concepts.n
- SDC constraints and UPF knowledge.n
- Scripting in Tcl, Python or Perl, plus Makefile-based flows.n

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nGood to Have
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- Full-cycle tapeout experience.n
- ARM-based SoC and AMBA protocols (AXI/AHB/APB).n
- Exposure to DFT, STA (PrimeTime) or LEC flows.n
- Education: BE/BTech/ME/MTech in ECE, EEE, VLSI or a related field.n
- Screening keywords for TA: VC SpyGlass, SpyGlass Lint/CDC/RDC, Questa CDC, Meridian CDC/RDC, VC LP, VCLP, Conformal LP, UPF, CPF, Design Compiler, Fusion Compiler, Genus, Formality, Conformal LEC, SD

📌 System-on-Chip Design Engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru