Location: Bengaluru
Experience: 4–10 years
Employment Type: Full-time
About the Role
We are looking for So C design engineers to own RTL integration and front-end signoff for complex So Cs. You will integrate IPs at subsystem and top level, and drive Lint, CDC, RDC, low-power (VCLP) and synthesis checks to closure for tapeout.
Key Responsibilities
So C integration: Integrate IPs at subsystem and top level, including clock, reset, memory, pad/IO and interconnect. Build and maintain top-level RTL and connectivity. Lint: Run Lint checks, analyze violations, drive fixes with IP owners, and manage waivers to signoff. CDC/RDC: Set up constraints, and analyze synchronizers, reconvergence, glitches and reset domain crossings. Deliver clean signoff reports. Low power (VCLP): Write and review UPF. Verify isolation, level shifters, retention and power switches using static low-power checks. Synthesis: Write SDC constraints, run synthesis, and improve timing, area and power Qo R. Run logic equivalence checks (RTL vs netlist). Collaboration:



Work with verification, DFT, STA and physical design teams through tapeout. Must-Have Skills
Solid Verilog/System Verilog RTL design and debug. Hands-on experience with at least three of: Lint, CDC, RDC, VCLP/UPF, synthesis, So C integration. Good understanding of clocking, reset architecture and low-power design concepts. SDC constraints and UPF knowledge. Scripting in Tcl, Python or Perl, plus Makefile-based flows. Good to Have
Full-cycle tapeout experience. ARM-based So C and AMBA protocols (AXI/AHB/APB). Exposure to DFT, STA (Prime Time) or LEC flows. Education: BE/BTech/ME/MTech in ECE, EEE, VLSI or a related field. Screening keywords for TA: VC Spy Glass, Spy Glass Lint/CDC/RDC, Questa CDC, Meridian CDC/RDC, VC LP, VCLP, Conformal LP, UPF, CPF, Design Compiler, Fusion Compiler, Genus, Formality, Conformal LEC, SDC, So C integration

📌 System-on-chip design engineer (Bengaluru)
🏢 leadIC Design
📍 Bengaluru