Job DescriptionSenior Memory Layout Engineer
NLocation: Bengaluru
NExperience: 4–10 Years
NRole Overview
nWe are looking for a Senior Memory Layout Engineer with strong hands-on expertise in memory/custom layout for advanced technology nodes, including 2nm, 3nm, and 5nm FinFET processes.
NKey Responsibilities
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- N
- Develop memory macro and custom layouts from floorplan through tapeout. N
- Work on SRAM bitcell, memory arrays, and peripheral circuit layouts. N
- Execute layout optimization for area, density, matching, parasitics, and performance. N
- Implement advanced-nodeFinFET layout techniques and design-rule requirements. N
- Perform and debug DRC, LVS, ERC, PEX and physical verification. N
- Analyze parasitic effects, EM/IR and layout-dependent effects. N
- Collaborate with MemoryDesign, Circuit Design, Physical Verification and Technology teams. N
- Support tapeout, signoff and post-layout correlation. N

nCore Technical Skills
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- n
- 4–10 years of Memory / Custom Layout experience. N
- Robust hands-on experience with 2nm / 3nm / 5nm FinFET technologies. N
- Expertise in SRAM / memory macro layout and advanced-node design rules. N
- Strong knowledge of matching, symmetry, shielding, guard rings and sensitive-net routing. N
- Proficiency in Cadence Virtuoso / Custom Layout. N
- Experience with Calibre/ PVS, DRC, LVS, ERC and PEX. N
- Strong understanding ofparasitic optimization and layout-dependent effects. N
- Advanced-node tapeout experience is highly preferred. N

nIdeal Profile: A hands-on memory layout engineer capable of delivering tapeout-quality SRAM/memory layouts at advanced FinFET nodes, with strong ownership of area, quality, parasitics and physical verification.

📌 Senior Memory Layout Engineer (Karnataka)
🏢 Leadsoc Technologies
📍 Karnataka