Job Description
Hi All,
n

nGreetings from Eximietas Design...
n

n???? We're Hiring | Staff DFT Engineers | Eximietas Design | Visakhapatnam
n

nLocations:
n
- n
- India: Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam. n

n

nSan Jose (Bay Area), USA
n
- n
- Eligibility (USA): U.S. Permanent Residents (Green Card holders).n

n

nExperience: 12+ Years
n

nJob Description:
nWe are seeking motivated Design for Test (DFT) professionals to join our growing team. You will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across complex IP, Subsystem, and SoC designs.
n

nKey Skills:
n✔ End-to-End DFT Flow Ownership.
n✔ Scan Insertion, EDT & OCC.
n✔ ATPG, DRC Analysis & Coverage Closure.
n✔ Pattern Simulation & Debugging.
n✔ SoC Integration & Pattern Retargeting.
n✔ MBIST, IJTAG & JTAG Implementation.
n✔ DFT Sign-off Activities.
n

nTools Expertise:
nSiemens Tessent.
nSynopsys TestMAX / TetraMAX.
nCadence Modus.
n

nPreferred Skills:
n✅ Streaming Scan Network (SSN).
n✅ Analog & Mixed-Signal DFT.




n✅ SpyGlass DFT.
n✅ RTL DFT Methodologies.
n✅ TCL, Python & Perl Scripting.
n

nCore Responsibilities:
n• End-to-end ownership of DFT implementation flow from RTL to sign-off.
n• Scan architecture implementation including EDT & OCC.
n• ATPG, DRC analysis, coverage optimization, and pattern simulations.
n• SoC integration, pattern retargeting, and DFT debugging.
n• MBIST, IJTAG, and Boundary Scan (JTAG) integration.
n• Collaboration with Design, Verification, and Physical Design teams.
n• DFT sign-off ownership and deliverables.
n

nTechnical Requirements:
n• Robust experience in ATPG simulations and netlist handling.
n• Expertise in block-level and SoC-level pattern retargeting/debugging.
n• Strong understanding of ICL and PDL standards.
n• Hands-on experience with Tessent, TestMAX/TetraMAX, or Modus.
n

nInterested candidates can share their updated resume at:
nContact:
n

n???? Referrals a

📌 Staff DFT Engineer_Visakhapatnam (Modavalasa)
🏢 Eximietas Design
📍 Modavalasa