Responsibilities:
- Strong expertise in low-power and ultra-low-power SoC implementation to lead power-intent validation and integration using UPF methodologies for ADI's advanced node designs.
- Ability to collaborate and resolve agile & static IR issues.
- Good exposure to high-frequency design convergence for PDN and descent exposure VCD flows, RHVoltus/Voltus, and Vmin flows.
- Evaluate and optimise different power distributions (voltage rail assignments, regulator assignment) for a SoC.
- Modelling the power delivery networks, including on-die power gating and in-rush current profiles.
- Modelling the current profiles and peak current demands of various IPs.
- Evaluate and optimise voltage rail assignment and regulator requirements for SOC.
- Working with the system, PMIC and silicon package team to model the voltage response of the power delivery network.
📌 Power Integrity and Validation Engineer (Bengaluru)
🏢 Modernize Chip Solutions (MCS)
📍 Bengaluru
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