Key Responsibilities
Own AMS verification for assigned IPs/subsystems from specification review through sign-off.
Develop and maintain wreal models for analog blocks.
Work closely with Analog Design and Digital teams to understand circuit intent and abstraction trade-offs.
Analyze failures across analog and digital domains and drive root-cause resolution.
Review and improve existing AMS testbenches and models.
Contribute to coverage closure, waiver reviews, and sign-off documentation.
Ensure verification quality across mixed-signal IPs.
Candidate Profile
46 years of hands-on experience in AMS Verification
Robust expertise in Verilog-AMS
Solid knowledge of SystemVerilog
Hands-on experience with wreal modeling
Experience with Xcelium AMS and/or VCS AMS
Good understanding of mixed-signal verification
Robust debugging and root-cause analysis skills