Job Description
RTL & FPGA Design Engineer
nExperience : 4-6 years
nLocation : Hyderabad
nCore Skills: RTL Digital Design (Verilog/VHDL), Vivado toolchain (Design creation to Bitstream generation), and timing/IO constraints.
nArchitecture & Interfaces: Solid grasp of AXI/AHB/CHI/ACE5 buses, peripherals (USB, Ethernet), and Video IPs (ISP/Encoder/Decoder).
nDebugging & Tools: Industry-standard front-end waveform debugging, ILA, Unix environment, and scripting (Tcl/Python/Perl).
nBonus: Hands-on experience with pre-silicon platforms and automated verification flows.
nInterested candidates, please send your resume to
[email protected]
📌 RTL - FPGA Design Engineer (Hyderabad)
🏢 ACL Digital
📍 Hyderabad