Job Description
Experience : 3+ Years
nNotice Period : Immediate to 30 days.
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nJob Description:
n* Placement/Power aware synthesis using Synopsys & Cadence tools (DCG/NXT/FC, Genus)
n* Constraints development, Formal Verification, CECO, Static Timing Analysis & timing closure
n* Work closely with design team to come up with preplacement requirements & timing constraints
n* Work closely with physical design team for floorplan, placement & timing reviews
n* Work closely with cross-functional teams to review standard cell profile, timing models & memory models
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nSkills:
n* Good understanding of ASIC design flow
n* Hands on experience in synthesis and static timing analysis
n* Proficiency with Synopsys DC & PT tools and Verilog/VHDL is a must
nExperience in Perl, TCL and shell scripting is desirable
n* Excellent interpersonal & analytical skills with ability to work independently
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nBachelors or Master's Degree with a robust VLSI Background

📌 Synthesis Engineer (Bengaluru)
🏢 Mirafra Technologies
📍 Bengaluru