Senior Design Lead

Bangalore, Karnataka

Job Summary

Standard Cell Layout Engineer to independently drive block-level layout design activities, ensuring high-quality execution and timely delivery. The role involves close collaboration with internal teams and customers. Providing training & Mentor junior engineers in ramp-up. Co-ordinate effectively with the customer & team-members, for the successful overall project execution.

Key Responsibilities

Independently execute block-level layout design (Onsite/Offshore), including:

Floorplanning as per area and top-level constraints

Parasitic-aware routing

Physical verification and sign-off

Ensure on-time delivery of layouts with required quality standards

Perform and debug physical verification checks (DRC, LVS, ERC, boundary conditions)

Collaborate effectively with customers and cross-functional teams for successful project execution

Guide and mentor junior team members, review their work and drive quality improvements

Contribute to project planning, tracking, and execution efficiency

Required Skills (Must-Have)

Should be able to lead a small size team

Should be able to setup flow from scratch

Strong understanding of CMOS and FinFET devices (characteristics, challenges, constraints)

Good knowledge of digital circuit design (combinational & sequential circuits)

Hands-on experience in:

Standard Cell Layout Design (CMOS & FinFET)

Physical verification flows (DRC, LVS, ERC, boundary checks) and debugging

Expertise in:

Floorplanning, routing,



and verification of standard cell libraries

EDA tools: Cadence Virtuoso XL, Calibre, PVS

Proficient in Cadence Virtuoso layout editor and associated PV flow

Good understanding of:

Standard cell schematics

Standard cell architectures

Basic exposure to scripting (SKILL / Shell / Perl / Python)

Desired Skills (Good-to-Have)

Experience in advanced technology nodes (<16nm / FinFET nodes)

Robust team collaboration and coordination skills across multiple teams

Good written and verbal communication skills

Positive attitude toward learning and adaptability

Education & Experience

B.Tech / M.Tech in Electronics / VLSI / Related field with 6–9 years of industry experience

Keywords

Standard Cell Design, Layout Design, Physical Verification, Cadence Virtuoso XL, Calibre, Characterization, View Generation, CMOS, FinFET

Key Responsibilities

1. To leverage design expertise to ensure that software and products exhibit user-friendliness, intuitiveness, and alignment with user expectations, contributing to the creation of seamless user experiences.
2. To lead a team of designers, provide guidance, and ensuring the delivery of high-quality design solutions in alignment with the overall business goals.
3. To present design concepts and play a crucial role in shaping the overall design vision and strategy.
4. To stay abreast of industry trends, emerging technologies to drive innovation and excellence in design.

📌 Senior Design Lead (India)
🏢 HCLTech
📍 India