Job DescriptionHi All, NGreetings from Eximietas Design...! NEximietas Hiring Principal SoC DFT Engineers | Bengaluru Location. NExperience: Min 10+Years. NLocations:- Bengaluru, Hyderabad, Ahmedabad & Visakhapatnam. NSan Jose (Bay Area), USA Nn Eligibility (USA): U.S. Permanent Residents (Green Card holders). NnJob Description: NWe are seeking motivated Design for Test (DFT) professionals to join our growing team. Whether Nyou are a hands-on technical lead or an industry veteran with architectural expertise, we offer roles Nthat will challenge and grow your skills in advanced silicon testing. NYou will be responsible for the end-to-end DFT flow, from RTL to final pattern delivery, across Ncomplex IP, subsystem, and SOC designs. NCore Responsibilities: N End-to-end ownership of the DFT implementation flow from RTL to final pattern sign-off. N Scan architecture definition and implementation at RTL and gate level, including EDT and NOCC.n Execution of block-level ATPG, DRC analysis, and coverage optimization. N Handling of pattern simulations, including both timing and non-timing simulations. N SOC-level integration, including pattern retargeting to subsystem and full-chip levels. N Integration, simulation,and debugging of MBIST, IJTAG, and Boundary Scan (JTAG). N Independent debugging ofDFT simulations and netlist-related issues. N Close collaboration withdesign, verification, and physical design teams to ensure DFT Nreadiness.n Ownership of DFT sign-off activities and deliverables. NKey Responsibilities: N Develop and implement robust DFT architectures for IP, subsystem, and SOC designs. N Perform scan insertion, ATPG generation,



and pattern validation at block and top levels. N Analyze and resolve coverage, DRC, and simulation failures to meet quality targets. N Define and execute DFT strategies aligned with project requirements and schedules. N Support pre-silicon and post-silicon test requirements. N Serve as the DFT point of contact for assigned projects, responsible for verification and test Nreadiness sign-off.nTechnical Requirements: NMust-Have Skills: N Strong experience in netlist handling and ATPG simulations. N Proven expertise in block-level and SOC-level pattern retargeting and debugging. N In-depth understanding of ICL and PDL standards. N Hands-on experience withat least one major DFT tool suite: No Siemens Tessentno Synopsys TestMAX / TetraMAX No Cadence ModusnPreferred & Advanced Skills: N Experience with Streaming Scan Network (SSN). N Knowledge of Analog and Mixed-Signal DFT methodologies. N Proficiency with SpyGlass for DFT linting and early-stage analysis. N Exposure to RTL-level DFT insertion and validation. N Strong scripting skills (TCL, Python, Perl) for automation. NWhat We Offer: Nn Opportunity to work on cutting-edge semiconductor designs and creative technologies. N Collaborative and inclusive work environment. N Competitive compensation and benefits package. N Professional growth anddevelopment opportunities. NnIf this opportunity interests you—or if you know someone suitable—please send your updated resume to: . NReferrals are highly appreciated. NBest regards,nMaruthy Prasaad NAssociate VLSI Manager - Talent Acquisition | Visakhapatnam NEximietas Designn n+91 (phone hidden).

📌 Principal Soc Dft Engineer_bengaluru (Karnataka)
🏢 Eximietas Design
📍 Karnataka