23 Sep
|
UST
|
Vasanthanagar
Job DescriptionHi,
nPlease find the JD below:-
n10+ years experience in Intel/Altera FPGAs (Agilex, Stratix‐10, Arria‐10)
n
- n
- Architecting FPGA systems with PCIe Gen4/Gen5 Hard IPn
- Expertise in Quartus Prime Pro, Platform Designer, timing closure, transceiver configurationn
- Experience with NVMe/PCIe protocols, DMA engines, and high‐speed digital designn
- Ownership of system architecture, FPGA design reviews, floorplanning, and integrationn
- Guide team on RTL quality, CDC, SDC constraints, SignalTap debug, and performance optimization.n
nKindly note: Altera FPGA and PCIe Gen 3/4/5 experience is mandatory.
nPlease do share your resume to or refer your friends or colleagues.
nRegards,
nJaya
📌 Opening for FPGA Design (Vasanthanagar)
🏢 UST
📍 Vasanthanagar