Are you looking for a unique prospect to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.
People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip's
nationally-recognized
Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our
Vision, Mission, and 11 Guiding Values
; we affectionately refer to it as the
Aggregate System
and it's won us countless awards for diversity and workplace excellence.
Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over
30 years of quarterly profitability
without a great team dedicated to empowering innovation. People like you.
Visit our
careers
page to see what exciting opportunities and company
perks
await!
Job Description:
Role Overview
The candidate will join Microchip's rapidly growing
Data Center Solutions (DCS)
business unit, delivering high-performance silicon solutions used by leading server and storage OEMs and hyperscale data centers. DCS products enable workloads ranging from
cloud and big data storage
to
AI/ML acceleration
,



shaping the next generation of data center infrastructure.
The DCS portfolio includes
SAS, PCIe, NVMe, and CXL infrastructure products
,
Flash Controllers
,
High-Performance Switches
, and
advanced memory infrastructure solutions
. This role provides a unique opportunity to drive
architecture, design excellence, and methodology innovation
in complex data center–class ASICs.
Key Responsibilities
Lead
architecture and micro-architecture definition
for complex IPs, subsystems, or full-chip designs.
Drive
end-to-end RTL design execution
, from concept through synthesis, sign-off, and silicon bring-up support.
Serve as a
technical authority
for digital design, ensuring high standards in quality, performance, power, and area (PPA).
Resolve
complex, cross-domain design and EDA tool challenges
impacting schedule or silicon quality.
Collaborate closely with
verification, physical design, DFT, system, and product teams
to ensure robust and predictable delivery.
Guide
low-power, high-performance design strategies
suitable for data center workloads.
Influence
protocol and platform roadmap decisions
, particularly in PCIe, CXL, NVMe, SAS, and related interconnects.
Mentor and technically guide
Senior and Staff engineers
, providing architectural reviews and design direction.
Represent the design organization in
technical reviews with senior leadership and cross-functional stakeholders




Identify opportunities to apply data driven approaches to improve design quality, efficiency and time-to-market
Define and enforce
design methodologies, sign-off criteria, and best practices
across projects.
Champion AI/ML-assisted
automation and intelligent workflows
that scale across teams and projects.
Requirements/Qualifications:
Bachelor degree in Electronics or Electrical Engineering minimum
15+ years
of experience in
ASIC or SoC digital design
.
Bachelor degree in Electronics or Electrical Engineering minimum
Strong expertise in
SystemVerilog RTL design
and micro-architecture development.
Proven success delivering
multiple complex tape-outs
in high-performance or data center–class silicon.
Deep hands-on experience with
Lint, CDC, formal verification, logic synthesis, and static timing analysis
.
Strong understanding of
physical design interactions
, including timing, power, and congestion considerations.
Solid experience with
low-power design methodologies and flows
.
Mandatory knowledge of DFT
, including scan, testability considerations, and DFT sign-off interactions.
Proficiency in
scripting languages
such as
Tcl, Perl, and/or Awk
.
Hands-on experience with
high-speed protocols
such as
PCIe, CXL, NVMe, SAS/SATA
, or similar serial interfaces.
Hands-on experience with
Cadence-based ASIC design environments
is an assset
Travel Time:
0% - 25%
To all recruitment agencies
:
Microchip Technology Inc.
does not
accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

📌 Senior Technical Staff Engineer - Design (Bengaluru)
🏢 Microchip
📍 Bengaluru