Position
Overview
We are seeking
a highly motivated IP/SoC Design Verification Engineer with strong expertise in
functional verification methodologies and SoC/IP validation. The ideal
candidate will be responsible for verifying complex ASIC/SoC designs and
ensuring first -time -right silicon quality for next -generation semiconductor
products.
The role requires
deep understanding of SystemVerilog, UVM -based verification environments,
protocol verification, and debugging across IP and SoC -level verification
flows.
Key
Responsibilities
Develop and execute verification plans for
both
IP and SoC -level designs.
Build reusable verification environments using
SystemVerilog and UVM methodology.
Develop test benches, assertions, checkers, coverage
models, and test cases.
Perform functional, regression, and coverage -driven
verification.
Debug RTL and verification environment issues to
identify root causes.
Collaborate closely with RTL Design, Architecture,
Firmware, and Validation teams.
Participate in design reviews and verification
closure activities.
Ensure verification quality through functional and
code coverage metrics.
Work on protocol and subsystem verification for
complex SoC designs.
Requirements




Required
Skills & Qualifications
Bachelor's or Master's degree in Electronics,
Electrical Engineering, VLSI, or related field.

4+ years of hands -on experience in IP/SoC
Verification.

Solid expertise in:

SystemVerilog

UVM Methodology

Functional Verification

ASIC/SoC Verification Flows

Experience in developing scalable and reusable
UVM -based verification environments.

Good understanding of:

Assertions (SVA)

Coverage -driven verification

Debugging methodologies

Simulation and regression flows

Strong debugging and analytical skills.

Familiarity with industry -standard EDA tools and
simulators.
Preferred
Skills
Experience verifying high -speed protocols such as:
PCIe
AXI/AHB/APB
Ethernet
USB
DDR
MIPI
Exposure to SoC integration verification.
Experience with scripting languages such as Python,
Perl, or Tcl.
Familiarity with low -power verification concepts.
Exposure to emulation/FPGA validation is an added
advantage.
Tools &
Technologies
SystemVerilog
UVM
VCS / Xcelium / Questa
Verdi / DVE
SpyGlass
Python / Perl / Tcl
Jenkins / Regression Automation Tools

📌 Design Verification Engineer (Both Ip And Soc Required) (Bengaluru)
🏢 Minutes to Seconds Pty
📍 Bengaluru