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Job Description:
Job Summary
We are looking for a highly motivated
Senior Engineer I – Design
with a strong understanding of
full-chip SoC architecture
to join our engineering team. This role requires hands-on expertise across both
RTL design and verification
, with responsibility for delivering high-quality,



fully verified designs from concept through tape-out. The ideal candidate combines deep technical knowledge with a system-level mindset, Latest AI know how and strong cross-functional collaboration skills.
Key Responsibilities
Contribute to
RTL design and verification
of complex SoC and full-chip designs with ARM cortex M0+ , RISCV and other cores.
Develop and review
micro-architecture and design specifications
Implement high-quality, synthesizable
RTL (Verilog/SystemVerilog)
Create and execute
verification plans
at block, subsystem, and full-chip levels
Develop and maintain
SystemVerilog/UVM-based verification environments
Drive functional, code, and assertion coverage closure
Debug and resolve issues across
design, integration, and full-chip bring-up
Collaborate with architecture, physical design, firmware, and validation teams
Support
clock, reset, power, and CDC/RDC
design and verification
Mentor junior engineers and contribute to design and verification best practices
AI- Skills
Leverage AI/ML tools to improve
RTL development, verification productivity, and debug efficiency.
Use and prompt LLM based
assistants to generate code, stimuli, documentation, root cause analysis and scripting
Apply AI driven techniques for log analysis, waveform triage and failure clustering
Ability to design, run, and analyze
AI‐assisted trials/experiments
to improve productivity or quality




Know-how of integrating AI tools with
existing EDA flows and scripts.
Soft Skills
Excellent written and verbal communication skills.
Strong analytical, debugging, and problem-solving abilities.
Self-motivated, detail-oriented, and quality-focused.
Ability to collaborate effectively across
global, cross-functional teams
.
Comfortable working in a fast-paced, evolving MCU product environment.
Requirements/Qualifications:
Required Qualifications
Bachelor's or Master's degree in
Electrical Engineering, or Electronics or VLSI
5+ years of experience in
ASIC/SoC design and verification
Strong expertise in
RTL design using Verilog/SystemVerilog
Solid experience with
SystemVerilog and C based coding
Strong understanding of
full-chip SoC architecture and integration
Experience with simulation, debugging, and coverage analysis tools
Proficiency in scripting languages such as
Python, Perl, or Shell
Excellent problem-solving, debugging, and communication skills
Preferred Qualifications
Experience with
full-chip integration and top-level verification
Knowledge of
low-power design and verification
(UPF/CPF)
Familiarity with
CDC/RDC analysis and timing concepts
Exposure to
AMS or mixed-signal interfaces
(e.g., PLLs, ADC/DAC)
Experience with
formal verification
techniques
Prior experience mentoring junior engineers or leading technical initiatives
Travel Time:
No Travel
To all recruitment agencies
:
Microchip Technology Inc.
does not
accept unsolicited agency resumes. Please do not forward resumes to our recruiting team or other Microchip employees. Microchip is not responsible for any fees related to unsolicited resumes.

📌 Senior Engineer I - Design (Chennai)
🏢 Microchip
📍 Chennai