Position:
Senior Engineer (level 1) - DFT
Job Description:
Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP Tests and Pattern validation w/wo Timing, DFT mode timing Analysis and sign off.
Be responsible for a comprehensive DFT plan
Incumbent to work with DFT and cross functional teams
To architect and implement solutions for Scan and built-in self-test (Memory and Logic BIST) circuitry to test devices in the field
Location:
IN-TG-Hyderabad, India-Gowra Palladium (eInfochips)
Time Type:
Full time
Job Category:
Engineering Services
📌 Senior Engineer (Level 1) - Dft (India)
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📍 India