Job Title :

Director of Digital Design Engineering, Memory Interface IP

We Are :

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services.

You Are :

You have spent years deep in the world of high-speed memory interfaces. You know HBM, DDR, and LPDDR as living systems. You have built teams that ship, and you know the difference between a group that executes and one that just stays busy. You do not manage from a distance; you review RTL, ask hard questions, and push back when a verification plan is too thin.

What You'll Be Doing :

- Lead a team of ASIC digital design and verification engineers working on HBM, DDR, and LPDDR memory interface IP
- Own the technical direction and execution of RTL design and verification at both block and chip integration levels
- Drive design reviews, architecture decisions, and quality checkpoints across the full development cycle from spec to silicon
- Collaborate with cross-functional teams including analog design, DFT, physical design, and product management
- Build and refine design and verification methodologies, incorporating AI-driven tools and automation
- Manage project timelines, resource allocation, and risk mitigation
- Mentor and develop engineers,



providing technical guidance and career growth opportunities The Impact You Will Have :
- Deliver memory interface IP that enables the next generation of AI accelerators, data center processors, and high-performance SoCs
- Raise the bar for design quality and verification coverage
- Shape the technical roadmap for high-speed memory controllers
- Build a high-performing team culture
- Accelerate time to market by driving adoption of advanced methodologies and AI-assisted design flows

What You'll Need :

- 15 - 20+ years of experience in ASIC digital design and verification, with significant hands-on work in memory interface IP such as HBM, DDR, or LPDDR
- Proven track record leading engineering teams through full product development cycles
- Deep expertise in RTL design, verification methodologies, and design closure
- Strong understanding of memory protocols, PHY/controller architecture, signal integrity, and timing closure
- Experience managing cross-functional collaboration
- Demonstrated ability to communicate technical risks and project status to executive leadership

Rewards and Advantages :

- We offer a comprehensive range of health, wellness, and financial benefits. Your recruiter will provide more details during the hiring process.

📌 Synopsys - Director - ASIC/RTL Design (India)
🏢 Synopsys
📍 India