{"company":"

About TylSemi, Inc.

The Opportunity The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package

Thats what we solve. TylSemi builds the chiplet infrastructure IP the IO, power delivery, and interconnect building blocks that makes AI/HPC systems actually work at scale.

This isnt a nice-to-have. Its the critical path.

Why Now The Market Window The semiconductor industry is going through its biggest architectural shift in 40 years:

Moores Law is dead. 2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.

Custom silicon is now mainstream. Google, Microsoft, Amazon, Meta, OpenAI theyre all designing their own ASICs. The $50B custom silicon market is growing 30% annually.

IO and power are the bottleneck. Solve hard problems and provide something which is a category in itself.

Translation: Were entering the market at exactly the moment when every major AI/HPC player needs what were building, and their alternatives are disappearing.

Culture Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

If you have an idea, we test it. If it works, we ship it.

No endless meetings, no PowerPoint presentations to convince middle management.

Remote-Friendly, Global Team

US team: Bay Area preferred, but we hire the best people regardless of location

India team: Building a world-class design center in Bangalore

Move Fast, Ship Real Products

Were not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. Were building to win.

What We Value

Ownership mindset. Youre not here to execute someone elses roadmap. Youre here to define it.

Bias for action. We move fast. Analysis paralysis doesnt fly here.

Deep technical expertise. This is hard engineering. We need people whove shipped real silicon and debugged real hardware.

Low ego,



high standards. We dont care about titles or politics. We care about results.

The Ask

If youre reading this, youre probably comfortable. You have a good job at a stable company with all the advantages.

Were asking you to walk away from that and bet on us.

Heres why you should:

The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what were building.

The team has done this before. Weve built and exited semiconductor companies at scale. This isnt our first rodeo.

The traction is de-risked. We have LOIs, strategic investors, and a explicit path to revenue.

The work is consequential. Youre not optimizing someones ad click-through rate. Youre building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if youre the kind of person who wants to take the shot, wed love to talk.

READY TO JOIN

","role":"

Role Overview

We are looking for a highly motivated Senior Engineer - EM/IR to join the Physical Design and Signoff team. In this role, you will be responsible for performing power integrity analysis including IR drop and electromigration (EM) checks for advanced-node SoC designs. You will work closely with Physical Design, Power, and Package teams to ensure robust power delivery network implementation and reliable signoff closure.

The ideal candidate should have strong fundamentals in power integrity analysis, signoff methodologies, and advanced-node implementation challenges.

What You ll Do

- Perform block-level and full-chip IR drop and electromigration (EM) analysis for advanced-node designs




- Analyze and debug static and agile IR violations to achieve power integrity signoff closure
- Collaborate with Physical Design, Floorplanning, CTS, Routing, and Package teams to optimize power delivery networks
- Run and interpret power integrity analysis across multiple operating conditions and scenarios
- Support EM analysis by evaluating current density, reliability limits, and thermal impacts
- Develop and improve IR/EM automation flows, scripts, and signoff methodologies
- Support tapeout activities and ensure clean IR/EM signoff delivery

What We re Looking For

- Bachelor s or Master s degree in Electronics, Electrical Engineering, or VLSI-related discipline
- 5+ years of experience in EM/IR analysis, power integrity, or Physical Design signoff roles
- Strong understanding of static and dynamic IR drop analysis, electromigration concepts, and power grid optimization
- Hands-on experience with industry-standard tools such as Cadence Voltus, Ansys RedHawk, or equivalent
- Good understanding of Physical Design flow including floorplanning, placement, CTS, routing, and extraction
- Proficiency in Tcl, Perl, Python, or Shell scripting for automation and flow enhancement

Good to Have

- Experience with advanced technology nodes such as 7nm, 5nm, or below
- Exposure to package-aware analysis, thermal analysis, and low-power methodologies
- Understanding of power-aware signoff methodologies and reliability verification flows

Success in This Role Looks Like

- Achieving clean IR/EM signoff with robust power integrity across all operating conditions
- Efficient identification and resolution of power integrity and reliability issues
- Improved productivity through automation and methodology enhancements
- Successful collaboration across cross-functional teams leading to timely tapeout execution

Location Hybrid / On-site - Bengaluru / Remote - India

"},"

Disclaimer: This job posting has been aggregated from external source. Role details, content, and availability are subject to change. Applicants are advised to confirm the latest information directly on the company website before applying.

📌 Sr Engineer - RV (EM/IR) (Bengaluru)
🏢 tylsemi
📍 Bengaluru