Job Summary

Job Area: Engineering Group, Hardware Engineering

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.

As a Qualcomm HW SoC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

We are seeking a seasoned Staff / Sr Staff Physical Design Engineer to provide technical leadership across block-level, die-level and chip-level physical implementation on advanced FinFET nodes. You will define and own the backend design methodology, champion Agentic AI integration into the PD flow, and mentor engineers across the team while interfacing directly with foundry, EDA vendors, and executive stakeholders.

Minimum Qualifications

- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC physical design, ECO, STA, physical verification, power analysis or related work experience.
- Master's degree in Science, Engineering, or related field and 3+ years of ASIC physical design, ECO, STA, physical verification, power analysis or related work experience.




- PhD in Science, Engineering, or related field and 2+ years of ASIC physical design, ECO, STA, physical verification, power analysis or related work experience.

Preferred Qualifications
- Master's degree in VLSI, Electrical / Electronic Engineering, Physics Engineering, Computer Engineering, or Computer Science with 3+ years of experience.
- Deep expertise in full chip and block level floor-planning, design implementation through place and route, ECO, STA, LEC / Timing / Power closure, and Physical Verification;
- Experience with power optimization (DVFS, multi-Vt, power domains, UPF/CPF)
- Advanced Shell, Python and TCL scripting: ability to architect large-scale SOC back-end automation frameworks and flow infrastructure
- Demonstrated experience or vision for applying Agentic AI methodologies to EDA challenges: autonomous agents, AI-driven optimization, LLM-assisted debugging
- Robust communication skills: ability to present methodology decisions, risk assessments, and tape-out readiness to senior management

Principal Duties and Responsibilities
- Leverages advanced ASIC knowledge and experience to define, model, design (digital, analog and/or mix signal), optimize, verify, validate and implement IP (block/SoC) development for a variety of high performance, high quality, low power products.

📌 SoC Physical Design Engineer (Senior To Principal) (Hyderabad)
🏢 Qualcomm
📍 Hyderabad