e are looking for a Physical Design Engineer with strong hands-on experience in Cadence Innovus to join our VLSI team. The candidate will be responsible for physical implementation activities from netlist to GDSII and working closely with design, timing, and signoff teams to achieve optimal PPA and design quality.
Key Responsibilities
- Execute complete Physical Design flow from netlist to GDSII.
- Hands-on experience with Cadence Innovus for physical implementation.
- Perform floorplanning, power planning, placement, CTS, routing, and optimization.
- Analyze and resolve timing, congestion, setup/hold, and DRC violations.
- Perform physical design optimization for PPA improvement.
- Work on ECO implementation and timing closure.
- Coordinate with STA, RTL, DFT, and signoff teams for design closure.
- Support IR/EM, DRC/LVS,
and other physical signoff activities.
- Debug implementation issues and ensure successful tape-out.
Required Skills
- 5+ years of experience in Physical Design / PnR.
- Robust hands-on experience in Cadence Innovus.
- Good understanding of Floorplan, Placement, CTS, Routing, and Optimization.
- Strong knowledge of STA concepts and timing closure.
- Experience in setup/hold analysis and ECOs.
- Good understanding of physical design signoff checks.
- Knowledge of TCL/Perl/Shell scripting is preferred.
- Experience with advanced/lower technology nodes will be an added advantage.