Join a team working on next-generation semiconductor products and complex SoC designs at advanced technology nodes. This is an opportunity to drive timing architecture, timing signoff methodology, and full-chip timing closure for high-performance silicon.
What You'll Bring:
- Strong expertise in Static Timing Analysis (STA) and Timing Signoff
- Hands-on experience with PrimeTime, MMMC, OCV/AOCV/POCV/LVF
- Full-chip timing closure and signoff ownership
- Experience with advanced nodes (7nm/5nm/3nm and below)
- Exposure to timing architecture and methodology development
- Multi-die, Chiplet, or 3D-IC timing experience is a plus
- Technical leadership and mentoring capabilities
Target Titles: Lead STA Engineer | Principal STA Engineer | Staff STA Engineer | Timing Architect | Timing Signoff Lead | Full-Chip Timing Lead If you're looking for a high-impact role where you can solve challenging timing problems and influence next-generation silicon designs, we'd love to connect with you. Share your profile to explore this chance.