Position: Senior FPGA Design Engineer

Experience: 8+ Years

Location: Bangalore / Hyderabad / Pune (as applicable)

Job Summary:

We are looking for an experienced Senior FPGA Design Engineer with 8+ years of hands-on experience in FPGA and Digital Design. The candidate should have strong expertise in RTL design, FPGA implementation, timing closure, high-speed interfaces, FPGA IP integration/porting, and functional verification.

Key Responsibilities

- Design, develop and implement FPGA-based digital systems using Verilog, SystemVerilog and/or VHDL.
- Develop RTL architecture, microarchitecture and synthesizable RTL based on system requirements.
- Perform FPGA implementation using AMD/Xilinx Vivado tools.
- Work with Xilinx UltraScale/UltraScale+ FPGA families.
- Perform ASIC / 3rd-party IP porting and adaptation to FPGA, including synthesis and implementation.
- Handle FPGA floorplanning, placement, routing and physical optimization.
- Drive timing closure, including timing analysis, constraint development and optimization.
- Perform STA, CDC and XDC constraint development/debugging.
- Analyze and resolve timing violations, resource utilization and implementation issues.
- Work with Xilinx GTH/GTY high-speed transceivers and associated protocols.
- Integrate and debug high-speed interfaces such as PCIe, USB 3.x/USB4, MIPI and DDR4/DDR5.




- Develop and execute functional verification using simulation and FPGA-based validation.
- Debug RTL and system-level issues using simulation, waveform analysis and hardware debug tools.
- Work closely with ASIC, firmware, verification, system and board-design teams for IP integration and system bring-up.
- Support FPGA prototype bring-up, debugging and validation on hardware.

Required Technical Skills

- 8+ years of experience in FPGA/Digital Design.
- Strong hands-on experience in Verilog / SystemVerilog / VHDL.
- Strong experience with AMD/Xilinx Vivado.
- Experience with UltraScale / UltraScale+ FPGA architectures.
- Strong knowledge of RTL design, synthesis, implementation and FPGA architecture.
- Hands-on experience with Timing Closure and Static Timing Analysis (STA).
- Good understanding of CDC/RDC concepts and clock-domain crossing techniques.
- Robust experience in XDC constraints and timing constraints.
- Experience in ASIC/3rd-party IP porting to FPGA.
- Experience with FPGA floorplanning and physical optimization.
- Knowledge of Xilinx GTH/GTY transceivers.
- Experience with one or more of PCIe, USB 3.x/USB4, MIPI, DDR4/DDR5.
- Experience with ModelSim/QuestaSim or equivalent simulation tools.
- Good understanding of UVM and functional verification methodologies.

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