- Strong knowledge of DFT tools such as

Synopsys DFT Compiler, TetraMAX/TestMAX ATPG, and Siemens/Mentor Tessent

.

- Hands-on experience in

Scan Insertion, ATPG, LBIST, MBIST, Boundary Scan

, and DFT sign-off.

- Good understanding of

Scan Chains, JTAG (IEEE 1149.1), IEEE 1500, and IEEE 1687 (IJTAG)

standards.

- Experience in

Memory BIST (MBIST)

and

Logic BIST (LBIST)

implementation and verification.

- Expertise in

Scan/DFT stitching at both block-level and full-chip hierarchical integration.

- Understanding of high-speed interface DFT requirements such as SERDES, PCIe, USB, Ethernet PHY, and protocol-level testability.

- Valuable knowledge of

STA and timing closure related to DFT implementation.

- Proficiency in

Verilog/VHDL and scripting languages such as

TCL, Python, or Perl

.

- Strong debugging skills for ATPG, scan, and silicon bring-up issues.

- Experience with RTL-to-GDSII design flow and collaboration with RTL, PD, and Validation teams.

Key Responsibilities

- Define and implement DFT architecture for complex SoCs, subsystems, and IPs.

- Perform scan insertion, ATPG generation, fault simulation,



coverage analysis

, and DFT sign-off.

- Develop and integrate

LBIST, MBIST, Boundary Scan, IEEE 1500, and IJTAG solutions

.

- Execute DFT stitching and hierarchical integration across multiple design partitions.

- Drive fault coverage closure and optimize test patterns for manufacturing quality.

- Collaborate with RTL, Physical Design, and Verification teams for DFT feature integration and timing closure.

- Support ATE pattern generation, validation, and production test enablement.

- Debug silicon bring-up issues and resolve scan/test-related failures.

- Develop automation scripts to improve DFT productivity and flow efficiency.

Preferred Skills

- Experience with advanced technology nodes (

7nm/5nm/3nm and below

).

- Familiarity with low-power DFT methodologies and UPF/CPF-based designs.

- Knowledge of compression techniques, EDT, OCC, and test access architecture.

- Exposure to automotive, networking, AI/ML, or high-performance compute SoCs.

📌 Senior DFT Engineer (Bengaluru)
🏢 Ad Astra Consultants
📍 Bengaluru