Company Description Chiplogic Technologies is an IP and product engineering services company founded in 2018, specializing in Semiconductor, Systems, IoT, and AI/ML domains. The organization focuses on delivering high-quality, dependable solutions ranging from concept-to-silicon semiconductor design to complete system implementations. Chiplogic offers offshore development centers (ODC) and full turnkey design services, including proof-of-concept work and IoT system integration.

The company also provides AI/ML solutions built around its proprietary VISARD™ (Video Synthesis And Real-time Dynamics) framework. Team members collaborate on cutting-edge technologies and end-to-end product development for global customers.

Role Description We are looking for an experienced SoC Verification Engineer with strong hands-on expertise in PCIe protocol verification. The engineer will be responsible for developing and executing verification strategies for complex SoC designs, including PCIe subsystems, processors, memories, interconnects and peripherals.

Key Responsibilities

- Develop and execute SoC and subsystem-level verification plans.
- Verify PCIe controller, endpoint and root complex functionality.
- Develop reusable testbenches using SystemVerilog and UVM.
- Create constrained-random and directed test cases for PCIe features.
- Perform C/C++-based SoC verification and firmware-driven validation.
- Verify PCIe enumeration, configuration space, link training and data transactions.
- Validate LTSSM states, power management, interrupts and error-handling scenarios.
- Verify SoC boot flows, memory maps, resets, clocks and interrupt functionality.
- Integrate and configure PCIe VIP within the verification environment.
- Develop assertions, scoreboards,



checkers and functional coverage models.
- Analyse regression failures and debug complex RTL, protocol and testbench issues.
- Track code and functional coverage and drive verification closure.
- Collaborate with RTL design, architecture, firmware and validation teams.

Required Skills
- 5+ years of hands-on ASIC/SoC design verification experience.
- Strong experience in SoC or subsystem-level verification.
- Solid understanding of PCIe architecture and protocol.
- Hands-on experience with PCIe Gen3, Gen4, Gen5 or later generations.
- Positive knowledge of PCIe transaction, data-link and physical layers.
- Experience with LTSSM, TLPs, DLLPs, configuration space, BARs, MSI/MSI-X, enumeration, flow control and error handling.
- Strong proficiency in SystemVerilog and UVM.
- Experience developing testbenches, test cases, sequences, monitors, scoreboards and coverage models.
- Hands-on experience with C/C++-based SoC test-case development.
- Good understanding of AXI, AHB or APB protocols.
- Strong debugging skills using simulation waveforms and logs.
- Experience with simulators such as VCS, Questa, Xcelium or equivalent.
- Experience with coverage-driven verification and regression management.

Preferred Skills
- Experience with PCIe VIP from Synopsys, Cadence or Siemens.
- Knowledge of PCIe Gen6 or Gen7 is an advantage.
- Experience with formal verification or assertion-based verification.
- Familiarity with ARM-based SoCs, cache coherency and interconnect technologies.
- Knowledge of low-power verification, UPF and power-management scenarios.
- Experience with post-silicon validation, emulation or FPGA prototyping is beneficial.

EducationBachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Science or a related discipline.

📌 Senior Design Verification Engineer (Bengaluru)
🏢 Chiplogic Technologies
📍 Bengaluru